ISE

I always wondered why things take so long. Now I know.

For the past month, I was working on a Python version of the XSTOOLs software. I wanted an easy route to cross-platform capabilities for Windows, linux and OSX, and interpreted Python provides that. And not needing a compiler makes it easier for my customers to modify the software for their systems.

Some people have commented that the 12 MHz clock on the XuLA FPGA board is too slow for practical use. What they've missed is the Spartan-3A FPGA has on-chip digital frequency synthesizers (DFS) that can multiply the clock to over 300 Mhz. To show how easy it is to do this, I've added another chapter on using the DFS to my new book about doing FPGA design using Xilinx ISE WebPACK and the XuLA board. It just takes a few lines of VHDL and you can have almost any clock frequency you want between 5 MHz and 320 MHz.*

I'm writing a new book about doing FPGA design using Xilinx ISE WebPACK and the XuLA board. I've reproduced the preface for the book below. Here are the important points:

• I'm currently writing the book. New chapters will be released as I write them. There are currently four chapters available that cover FPGA basics, ISE compiler flow basics, entering VHDL, synthesizing, simulating, implementing, downloading and running a simple LED blinker design. Additional planned topics are listed in the preface.
• The book is covered under a Creative Commons Attribution-Sharealike 3.0 Unported license and stored on Github. So anyone can grab it, modify it, sell it, or whatever as long as they leave the other author names and affiliations intact and offer it freely with the same rights they got.
• I'm using FOSS tools like LibreOffice/OpenOffice and Inkscape for creating the text, so nobody will have to buy any tools if they want to modify it.