As FPGAs work their way into the hobbyist/maker community, I'm guessing a lot of you are trying to learn VHDL and Verilog. (You can try to use schematics, but the Xilinx editor is pretty poor.) Which language you choose is up to you, but I'll only talk about VHDL in this post. There's general agreement that if you know one, it's easy to learn the other.
There's no shortage of VHDL books (around 100 on Amazon) or online tutorials (Google lists 278,000 but I haven't checked them all), so there's no need for me to waste my energy doing another. Instead, what I will do is tell you how to use the existing books & tutorials to learn the use of VHDL in synthesizing logic for FPGAs.